In most wireless communication systems, the baseband signal at the receiver needs to be converted from analog format into digital format so that useful information can be recovered via a sequence of digital processes. The common device that achieves this conversion is an analog-to-digital converter (ADC). Given the number of output bits of the ADC, if the power of the input signal is too large, the output of the ADC may be saturated. On the other hand, if the power of the input signal is too small, the input signal may be severely quantized. In both cases, the information to be recovered at the received end may be lost. A common approach to solve this problem is to apply a dynamically adjustable gain amplifier in front of the ADC so that the input signal of the ADC can be maintained at a desired level.
Typically, the adjustable gain is controlled using a closed-loop mechanism, as shown in FIG. 1, which is also called an AGC 100. The AGC 100 includes two gain-adjustable amplifiers 105A and 105B, two ADCs 110A and 110B, a digital signal power estimator 115, a power comparator 120 and an accumulator 125. If the gain-adjustable amplifiers are controlled by an analog signal, a digital-to-analog converter (DAC) (not shown) may be inserted between the accumulator 125 and the gain-adjustable amplifiers 105A and 105B, or the DAC may be incorporated within the amplifiers 105A and 105B.
The gain-adjustable amplifiers 105A and 105B amplify or attenuate in-phase signal I and quadrature baseband signal Q. Signal I is received via an input 130 of gain-adjustable amplifier 105A and signal Q is received via an input 135 of gain-adjustable amplifier 105B. The ADCs 110A, 110B convert the amplified or attenuated analog signals and convert them into digital format.
Referring still to FIG. 1, the digital signal power estimator 115 estimates the total power of the digital signal at the output of power estimator 115. The comparator 120 compares the estimated digital signal input power 140 output from power estimator 115 with a power reference value Pref 145 and generates an error signal 150 which represents the difference between the estimated input signal power 140 and the power reference value Pref 145. The error signal 150 is then accumulated by the accumulator 125. Accumulator 125 outputs a gain control signal 155 having a control word w which is used to control the gain of the gain-adjustable amplifiers 105A, 105B. The gain control signal 155 depends not only on the power errors accumulated over time, but also on the initial value of the accumulator 125.
In many conventional digital communication systems, the input signal of an AGC is a continuous and smooth signal waveform. The power variation of the input signal is usually due to channel fading or power control and, therefore, such a power variation is slow relative to the dynamics of the AGC loop. Under this condition, the AGC loop will operate continuously without any interruption and the initial value of the accumulator is not important.
For digital communication systems using time division duplex (TDD) technology, there is a potentially large slot-to-slot variation of the received power, as shown in FIG. 2. This slot-to-slot power variation is primarily due to the fact that the systems using TDD technology can flexibly change the number of data bursts, which are spread with different codes and superimposed together in each time slot, over time. Owing to this power variation, the AGC 100 is required to be able to set the gain in front of the ADCs 110A, 110B quickly and correctly. Otherwise, the data at the beginning of the time slot may be lost due to either saturation or severe quantization. To meet this requirement, the accumulator 125 must be restarted with an accurate initial value such that an initial gain control signal is provided to the gain-adjustable amplifiers 105A, 105B at the beginning of each time slot. The initial gain value of the gain-adjustable amplifiers 105A, 105B directly depends upon the initial value provided by the accumulator 125.
What is needed is a method and apparatus to accurately determine the initial value of the accumulator 125 at the beginning of each uplink time slot at the base station, based on the level of information available at the base station.